QT320-IS View Datasheet(PDF) - Quantum Research Group
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QT320-IS Datasheet PDF : 18 Pages
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When SC=0 (no sleep cycles), the sensor operates without a
fixed timing and the acquisition spacing Tbs is the sum of the
burst durations for both channels (Figure 1-10). In this mode
of operation, Tbs and Tbd are the same value.
2 - CONTROL & PROCESSING
All acquisition functions are digitally controlled and can be
altered via the cloning process.
1.5.3 MAX ON-DURATION, TMOD
The Max On-Duration is the amount of time required for a
continuously detecting sense channel to recalibrate itself. This
parameter is user settable by changing MOD and SC (Section
2.6).
Tmod restarts if the OUT pin becomes inactive.
A recalibration of one channel has no effect on the other;
Tmod operates independently for each channel.
1.5.4 RESPONSE TIME, TDET
Response time from the onset of detection to an actual OUT
pin becoming active depends on:
Ti Basic Timing Interval
SC Sleep Cycles
(user setting)
DIT Detection Integrator Target (user setting)
DIS Detect Integration Speed (user setting)
Tbd Burst duration
(if DIS is set too fast)
Ti depends in turn on Vdd.
Signals are processed using 16 bit integers, using
Quantum-pioneered algorithms specifically designed to
provide for high survivability.
2.1 SLEEP CYCLES (SC)
Range: 0..255; Default: 1
Affects speed & power of entire device.
Refer to Section 1.5.1 for more information on the effect of
Sleep Cycles.
SC changes the number of intervals Ti separating two
consecutive burst pairs (Figure 1-10). SC = 0 disables sleep
intervals and bursts are crowded together with a rep rate that
depends entirely on the burst lengths of both channels
(Section 1.5.2).
Response time, drift compensation rate, max on-duration, and
power consumption are all affected by this parameter. A high
value of SC will make the sensor very low power and very
slow.
If the control bit DIS is normal (0), then Tdet depends on the
rate at which the bursts are acquiring, and the value of DIT. A
DIT number of bursts must confirm the detection before the
OUT line becomes active:
Tdet = SC x Ti x DIT
(normal DIS)
If DIS is set to fast, then Tdet also depends on BL:
Tdet = (SC x Ti) + (DIT-1)*Tbd (fast DIS)
Ti depends in turn on Vdd; Tbd depends on Cs and Cx for
both channels.
Quantum’s QT3View software calculates an estimate of
response time based on these parameters.
2.2 DRIFT COMPENSATION (PDC, NDC)
Signal drift can occur because of changes in Cx, Cs, Vdd,
electrode contamination and aging effects. It is important to
compensate for drift, otherwise false detections and sensitivity
shifts can occur.
Drift compensation is performed by making the signal’s
reference level slowly track the raw signal while no detection
is in effect. The rate of adjustment must be performed slowly,
otherwise legitimate detections could be affected. The device
compensates using a slew-rate limited change to the signal
reference level; the threshold and hysteresis points are slaved
to this reference.
1.6 EXTERNAL RECALIBRATION
The QT320 has no recalibration pin; a forced recalibration is
accomplished only when the device is powered up. However,
supply drain is low enough that the IC can be powered from a
logic gate or I/O pin of an MCU; driving the Vdd pin low and
high again can serve as a forced recalibration. The source
resistance of many CMOS gates and MCU’s are
low enough to provide direct power without
problems. A 0.01uF minimum bypass capacitor is
required directly across Vdd to Vss.
Once an object is detected, drift compensation stops since a
legitimate signal should not cause the reference to change.
Positive and negative drift compensation rates (PDC, NDC)
can be set to different values (Figure 2-1). This is invaluable
for permitting a more rapid reference recovery after a channel
has recalibrated while an object was present and then
removed.
lQ
Figure 2-1 Drift Compensation
7
QT320/R1.03 08/02
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