ST72251
Table 3. Hardware Register Memory Map
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh to
001Fh
0020h
0021h
0022h
0023h
0024h
0025h to
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h-0035h
0036h-0037h
0038h-0039h
003Ah-003Bh
003Ch-003Dh
003Eh-003Fh
0040h
Block
Name
Port C
Port B
Port A
SPI
WDG
I2C
Timer A
Register Label
Register name
Reset Status
PCDR
PCDDR
PCOR
PBDR
PBDDR
PBOR
PADR
PADDR
PAOR
Data Register
00h
Data Direction Register
00h
Option Register
00h
Reserved Area (1 Byte)
Data Register
00h
Data Direction Register
00h
Option Register
00h
Reserved Area (1 Byte)
Data Register
00h
Data Direction Register
00h
Option Register
00h
Reserved Area (21 Bytes)
MISCR
Miscellaneous Register
00h
SPIDR
Data I/O Register
xxh
SPICR
Control Register
0xh
SPISR
Status Register
00h
WDGCR
Watchdog Control register
7Fh
Reserved Area (3 Bytes)
I2CCR
Control Register
00h
I2CSR1
Status Register 1
00h
I2CSR2
Status Register 2
00h
I2CCCR
Clock Control Register
00h
I2COAR1
Own Address Register 1
00h
I2COAR2
Own Address Register 2
40h
I2CDR
Data Register
00h
Reserved Area (2 Bytes)
TACR2
Control Register2
00h
TACR1
Control Register1
00h
TASR
Status Register
00h
TAIC1HR
Input Capture1 High Register
xxh
TAIC1LR
Input Capture1 Low Register
xxh
TAOC1HR
Output Compare1 High Register
80h
TAOC1LR
Output Compare1 Low Register
00h
TACHR
Counter High Register
FFh
TACLR
Counter Low Register
FCh
TAACHR
Alternate Counter High Register
FFh
TAACLR
Alternate Counter Low Register
FCh
TAIC2HR
Input Capture2 High Register
xxh
TAIC2LR
Input Capture2 Low Register
xxh
TAOC2HR
Output Compare2 High Register
80h
TAOC2LR
Output Compare2 Low Register
00h
Reserved Area (1 Byte)
Remarks
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
10/100
9