PIC18F010/020
15.4.2 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 15-6:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
OSC1
CLKOUT
1
3
3
2
Q4
Q1
4
4
TABLE 15-3: EXTERNAL CLOCK TIMING REQUIREMENTS
Param. No. Sym
Characteristic
Min Typ† Max Units
Conditions
FOSC External CLKIN Frequency
DC —
4 MHz RC osc mode
(Note 1)
DC —
4 MHz XT osc mode
DC —
25 MHz HS osc mode
DC —
40 MHz EC osc mode
DC —
200 kHz LP osc mode
Oscillator Frequency
DC —
4 MHz RC osc mode
(Note 1)
0.1 —
4 MHz XT osc mode
4
—
25 MHz HS osc mode
4
—
8.25 MHz HS osc mode
5
—
200 kHz LP osc mode
1
TOSC External CLKIN Period
250 —
—
ns RC osc mode
(Note 1)
100 —
—
ns XT osc mode
40 —
—
ns HS osc mode
120 —
—
ns HS osc mode
30 —
—
ns EC osc mode
5
—
—
µs LP osc mode
Oscillator Period
250 —
—
ns RC osc mode
(Note 1)
0.1 —
10
µs XT osc mode
40 —
100 ns HS osc mode
120 —
100 ns HS osc mode
5
—
—
µs LP osc mode
2
TCY Instruction Cycle Time
100 Tcy
DC
ns TCY = 4/System Clock,
(Note 1)
40 MHz max
3
TosL, External Clock in (OSC1) High 30 —
—
ns XT oscillator
TosH or Low Time
2.5 —
—
µs LP oscillator
10 —
—
ns HS oscillator
4
TosR, External Clock in (OSC1) Rise — —
20
ns XT oscillator
TosF or Fall Time
——
50
ns LP oscillator
——
7.5 ns HS oscillator
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time limit is
"DC" (no clock) for all devices.
DS41142A-page 152
Preliminary
2001 Microchip Technology Inc.