ST62T09LD1/SWD Ver la hoja de datos (PDF) - STMicroelectronics

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ST62T09LD1/SWD

8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET

STMicroelectronics 

ST6208C/ST6209C/ST6210C/ST6220C

Opcode Map Summary (Continued)

LOW

8

1000

HI

9

1001

A

1010

0

0000

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

1

0001

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

2

0010

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

3

0011

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

4

0100

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

5

0101

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

6

0110

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

7

0111

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

8

1000

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

9

1001

2 RNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

A

1010

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

B

1011

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

C

1100

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

D

1101

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

E

1110

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

F

1111

2 JRNZ 4

JP 2 JRNC 4

e

abc

e

1

pcr 2

ext 1

pcr 2

B

1011

RES 2

b0,rr

b.d 1

SET 2

b0,rr

b.d 1

RES 2

b4,rr

b.d 1

SET 2

b4,rr e

b.d 1

RES 2

b2,rr

b.d 1

SET 2

b2,rr

b.d 1

RES 2

b6,rr

b.d 1

SET 2

b6,rr

b.d 1

RES 2

b1,rr

b.d 1

SET 2

b1,rr

b.d 1

RES 2

b5,rr

b.d 1

SET 2

b5,rr

b.d 1

RES 2

b3,rr

b.d 1

SET 2

b3,rr

b.d 1

RES 2

b7,rr

b.d 1

SET 2

b7,rr

b.d 1

C

1100

JRZ 4

e

pcr 3

JRZ 4

e

pcr 1

JRZ 4

e

pcr

JRZ 4

pcr 1

JRZ 2

e

pcr 1

JRZ 4

e

pcr 1

JRZ 2

e

pcr 1

JRZ 4

e

pcr 1

JRZ

e

pcr

JRZ 4

e

pcr 1

JRZ 4

e

pcr 1

JRZ 4

e

pcr 1

JRZ 2

e

pcr 1

JRZ 4

e

pcr 1

JRZ 2

e

pcr 1

JRZ 4

e

pcr 1

D

1101

LDI 2

rr,nn

imm 1

DEC 2

x

sd 1

COM 2

a

1

LD 2

x,a

sd 1

RETI 2

inh 1

DEC 2

y

sd 1

STOP 2

inh 1

LD 2

y,a

sd 1

2

#

1

DEC 2

v

sd 1

RCL 2

a

inh 1

LD 2

v,a

sd 1

RET 2

inh 1

DEC 2

w

sd 1

WAIT 2

inh 1

LD 2

w,a

sd 1

E

1110

JRC 4

e

prc 1

JRC 4

e

prc 2

JRC 4

e

prc 1

JRC 4

e

prc 2

JRC 4

e

prc 1

JRC 4

e

prc 2

JRC 4

e

prc 1

JRC 4

e

prc 2

JRC 4

e

prc 1

JRC 4

e

prc 2

JRC 4

e

prc 1

JRC 4

e

prc 2

JRC 4

e

prc 1

JRC 4

e

prc 2

JRC 4

e

prc 1

JRC 4

e

prc 2

LOW

F

1111

HI

LD

a,(y)

ind

0

0000

LD

a,rr

dir

1

0001

CP

a,(y)

ind

2

0010

CP

a,rr

dir

3

0011

ADD

a,(y)

ind

4

0100

ADD

a,rr

dir

5

0101

INC

(y)

ind

6

0110

INC

rr

dir

7

0111

LD

(y),a

ind

8

1000

LD

rr,a

dir

9

1001

AND

a,(y)

ind

A

1010

AND

a,rr

dir

B

1011

SUB

a,(y)

ind

C

1100

SUB

a,rr

dir

D

1101

DEC

(y)

ind

E

1110

DEC

rr

dir

F

1111

Abbreviations for Addressing Modes: Legend:

dir Direct

# Indicates Ill egal Instructions

sd Short Direct

e 5-bit Displacement

imm Immediate

b 3-bit Address

inh Inherent

rr 1-byte Data space address

ext Extended

nn 1-byte immediate data

b.d Bit Direct

abc 12-bit address

bt Bit Test

ee 8-bit Displacement

pcr Program Counter Relative

ind Indirect

Cycles

Operands

Bytes

2

JRC

e

1

prc

Addressing Mode

Mnemonic

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