ST72652 Ver la hoja de datos (PDF) - STMicroelectronics
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ST72652 Datasheet PDF : 166 Pages
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ST7265x
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
I2C CLOCK CONTROL REGISTER (CCR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0
Bit 7 = FM/SM Fast/Standard I2C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
0: Standard I2C mode
1: Fast I2C mode
Bit 6:0 = CC6-CC0 7-bit clock divider.
These bits select the speed
pending on the I2C mode.
of the bus (FSCL) de-
They are not cleared
when the interface is disabled (PE=0).
– Standard mode (FM/SM=0): FSCL <= 100kHz
FSCL = FCPU/(2x([CC6..CC0]+2))
– Fast mode (FM/SM=1): FSCL > 100kHz
FSCL = FCPU/(3x([CC6..CC0]+2))
Note: The programmed FSCL assumes no load on
SCL and SDA lines.
I2C DATA REGISTER (DR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7:0 = D7-D0 8-bit Data Register.
These bits contains the byte to be received or
transmitted on the bus.
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the next data bytes are received one by
one after reading the DR register.
Table 34. I2C Register Map
Address
(Hex.)
40
41
42
43
46
Register
Name
CR
Reset Value
SR1
Reset Value
SR2
Reset Value
CCR
Reset Value
DR
Reset Value
7
0
EVF
0
0
FM/SM
0
DR7
0
6
0
0
0
CC6
0
DR6
0
5
PE
0
TRA
0
0
CC5
0
DR5
0
4
0
0
AF
0
CC4
0
DR4
0
3
START
0
BTF
0
0
CC3
0
DR3
0
2
ACK
0
0
0
CC2
0
DR2
0
1
STOP
0
M/IDL
0
0
CC1
0
DR1
0
0
ITE
0
SB
0
0
CC0
0
DR0
0
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