STM32F103T4 Ver la hoja de datos (PDF) - STMicroelectronics
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STM32F103T4 Datasheet PDF : 123 Pages
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STM32F103xC, STM32F103xD, STM32F103xE
Description
Figure 2. Clock tree
OSC_OUT
OSC_IN
OSC32_IN
OSC32_OUT
USB
Prescaler
/1, 1.5
48 MHz
USBCLK
to USB interface
I2S3CLK
to I2S3
Peripheral clock
enable
I2S2CLK
to I2S2
8 MHz
HSI RC
HSI
/2
PLLSRC PLLMUL
..., x16
x2, x3, x4
PLL
Peripheral clock
enable
Peripheral clock
SDIOCLK to SDIO
enable
Peripheral clock
FSMCCLK to FSMC
enable
72 MHz max
HCLK
to AHB bus, core,
Clock
memory and DMA
SW
Enable (4 bits)
/8
to Cortex System timer
FCLK Cortex
HSI
PLLCLK
HSE
SYSCLK AHB
72 MHz Prescaler
max /1, 2..512
APB1
Prescaler
/1, 2, 4, 8, 16
free running clock
36 MHz max
PCLK1
to APB1
Peripheral Clock peripherals
Enable (20 bits)
CSS
TIM2,3,4,5,6,7
If (APB1 prescaler =1) x1
else x2
to TIM2,3,4,5,6 and 7
TIMXCLK
Peripheral Clock
Enable (6 bits)
4-16 MHz
HSE OSC
PLLXTPRE
/2
LSE OSC
32.768 kHz
/128
LSE
to RTC
RTCCLK
APB2
Prescaler
/1, 2, 4, 8, 16
72 MHz max
PCLK2
peripherals to APB2
Peripheral Clock
Enable (15 bits)
TIM1 & 8 timers
If (APB2 prescaler =1) x1
to TIM1 and TIM8
else x2
TIMxCLK
Peripheral Clock
ADC
Prescaler
/2, 4, 6, 8
Enable (2 bit)
to ADC1, 2 or 3
ADCCLK
LSI RC
40 kHz
RTCSEL[1:0]
LSI
to Independent Watchdog (IWDG)
IWDGCLK
/2
HCLK/2
To SDIO AHB interface
Peripheral clock
enable
MCO
Main
/2
Clock Output
MCO
PLLCLK
HSI
HSE
SYSCLK
Legend:
HSE = High Speed External clock signal
HSI = High Speed Internal clock signal
LSI = Low Speed Internal clock signal
LSE = Low Speed External clock signal
ai14752b
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
48 MHz or 72 MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
Doc ID 14611 Rev 7
13/123
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