STM32F103VC Ver la hoja de datos (PDF) - STMicroelectronics
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STM32F103VC Datasheet PDF : 123 Pages
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Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
I2S - SPI characteristics
Unless otherwise specified, the parameters given in Table 52 for SPI or in Table 53 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 10.
Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 52. SPI characteristics(1)
Symbol
Parameter
Conditions
Min Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
Slave mode
18
MHz
18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
DuCy(SCK)
SPI slave input clock duty
cycle
Slave mode
30
70
%
tsu(NSS)(2) NSS setup time
Slave mode
4tPCLK
th(NSS)(2) NSS hold time
Slave mode
2tPCLK
tw(SCKH)(2)
tw(SCKL)(2)
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
60
tsu(MI) (2)
tsu(SI)(2)
Data input setup time
Master mode
Slave mode
5
5
th(MI) (2)
Master mode
5
Data input hold time
th(SI)(2)
Slave mode
4
ta(SO)(2)(3) Data output access time Slave mode, fPCLK = 20 MHz
0
tdis(SO)(2)(4) Data output disable time Slave mode
2
tv(SO) (2)(1) Data output valid time
Slave mode (after enable edge)
tv(MO)(2)(1) Data output valid time
Master mode (after enable edge)
th(SO)(2)
th(MO)(2)
Data output hold time
Slave mode (after enable edge) 15
Master mode (after enable edge) 2
ns
3tPCLK
10
25
5
1. Remapped SPI1 characteristics to be determined.
2. Based on characterization, not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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Doc ID 14611 Rev 7
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