PIC18LF4523T-I/SO Ver la hoja de datos (PDF) - Microchip Technology

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PIC18LF4523T-I/SO

28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2423/2523/4423/4523

2.6 A/D Conversions

Figure 2-4 shows the operation of the A/D Converter

after the GO/DONE bit has been set and the

ACQT<2:0> bits are cleared. A conversion is started

after the following instruction to allow entry into Sleep

mode before the conversion begins.

Figure 2-5 shows the operation of the A/D Converter

after the GO/DONE bit has been set, the ACQT<2:0>

bits have been set to ‘010’ and a 4 TAD acquisition time

has been selected before the conversion starts.

Clearing the GO/DONE bit during a conversion will abort

the current conversion. The A/D Result register pair will

NOT be updated with the partially completed A/D

conversion sample. This means, the ADRESH:ADRESL

registers will continue to contain the value of the last

completed conversion (or the last value written to the

ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

2 TCY wait is required before the next acquisition can

be started. After this wait, acquisition on the selected

channel is automatically started.

Note:

The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Code should wait at least 3 TAD after

enabling the A/D before beginning an

acquisition and conversion cycle.

2.7 Discharge

The discharge phase is used to initialize the value of

the holding capacitor. The array is discharged before

every sample. This feature helps to optimize the unity-

gain amplifier, as the circuit always needs to charge the

capacitor array, rather than charge/discharge based on

previous measure values.

FIGURE 2-4:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

TCY – TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD1

b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Conversion starts

Holding capacitor is disconnected from analog input (typically 100 ns)

Discharge

(typically 200 ns)

Set GO/DONE bit

On the following cycle:

ADRESH:ADRESL are loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

FIGURE 2-5:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

TACQT Cycles

TAD Cycles

1234

Automatic

Acquisition

Time

1 2 3 4 5 6 7 8 9 10 11 12 13 TAD1

b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Conversion starts

(Holding capacitor is disconnected)

Points to end of TACQT period (current black arrow)

Discharge

(typically

200 ns)

Set GO/DONE bit

(Holding capacitor continues

acquiring input)

On the following cycle:

ADRESH:ADRESL are loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

© 2009 Microchip Technology Inc.

DS39755C-page 33

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