FDC37B78X Ver la hoja de datos (PDF) - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

NAME

Forced Disk

Change

Default = 0x03

on VTR POR

Floppy Data Rate

Select Shadow

UART1 FIFO

Control Shadow

REG

INDEX

0xC1 R/W

DEFINITION

Force Change 1 and Force Change 0 can be

written to 1 are not clearable by software.

Force Change 1 is cleared on (nSTEP AND nDS1)

Force Change 0 is cleared on (nSTEP AND

nDS0).

DSK CHG (Floppy DIR Register, Bit 7) = (nDS0

AND Force Change 0) OR (nDS1 AND Force

Change 1) OR nDSKCHG.

Setting either of the Force Disk Change bits active

(1) forces the FDD nDSKCHG input active when

the appropriate drive has been selected.

0xC2 R

0xC3 R

Bit[0] Force Change for FDC0

0=Inactive

1=Active

Bit[1] Force Change for FDC1

0=Inactive

1=Active

Bit[2:7] Reserved, Reads 0

Floppy Data Rate Select Shadow Register

Bit[7] Soft Reset

Bit[6] Power Down

Bit[5] Reserved

Bit[4] PRECOMP 2

Bit[3] PRECOMP 1

Bit[2] PRECOMP 0

Bit[1] Data Rate Select 1

Bit[0] Data Rate Select 0

UART1 FIFO Control Shadow Register

Bit[7] RCVR Trigger MSB

Bit[6] RCVR Trigger LSB

Bit[5] Reserved

Bit[4] Reserved

Bit[3] DMA Mode Select

Bit[2] XMIT FIFO Reset

Bit[1] RCVR FIFO Reset

Bit[0] FIFO Enable

STATE

201

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