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M25P05VMN6T

512 Kbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface

STMicroelectronics 

M25P05

Figure 14. Sector Erase (SE) Sequence

S

0123456789

29 30 31

C

Instruction

24 Bit Address

D

23 22

210

MSB

AI03751C

Note: 1. Address bits A23 to A16 must be set to 00h.

Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh)

all bits inside the chosen sector. Before it can be

accepted, a Write Enable (WREN) instruction

must previously have been executed. After the

Write Enable (WREN) instruction has been decod-

ed, the device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, and three address bytes on Serial

Data Input (D). Any address inside the Sector (see

Table 3) is a valid address for the Sector Erase

(SE) instruction. Chip Select (S) must be driven

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 14.

Chip Select (S) must be driven High after the

eighth bit of the last address byte has been latched

in, otherwise the Sector Erase (SE) instruction is

not executed. As soon as Chip Select (S) is driven

High, the self-timed Sector Erase cycle (whose du-

ration is tSE) is initiated. While the Sector Erase cy-

cle is in progress, the Status Register may be read

to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the

self-timed Sector Erase cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enable Latch (WEL)

bit is reset.

A Sector Erase (SE) instruction applied to a page

which is protected by the Block Protect (BP1, BP0)

bits (see Table 2) is not executed.

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