STM32F205RF Ver la hoja de datos (PDF) - STMicroelectronics

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Fabricante

STM32F205RF

ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

Electrical characteristics

STM32F20xxx

Figure 59. Synchronous multiplexed PSRAM write timings

tw(CLK)

tw(CLK)

FSMC_CLK

FSMC_NEx

td(CLKL-NADVL)

FSMC_NADV

FSMC_A[25:16]

FSMC_NWE

td(CLKL-ADV)

FSMC_AD[15:0]

Data latency = 0

td(CLKL-NExL)

td(CLKL-NADVH)

td(CLKL-AV)

td(CLKL-NWEL)

td(CLKL-ADIV)

td(CLKL-Data)

AD[15:0]

td(CLKL-Data)

D1

BUSTURN = 0

td(CLKL-NExH)

td(CLKL-AIV)

td(CLKL-NWEH)

D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

tsu(NWAITV-CLKH)

FSMC_NBL

th(CLKH-NWAITV)

td(CLKL-NBLH)

Table 75. Synchronous multiplexed PSRAM write timings(1)(2)

Symbol

Parameter

Min

tw(CLK)

FSMC_CLK period

td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)

td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low

td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high

td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25)

td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25)

td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low

td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high

td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid

td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low

td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high

1. CL = 30 pF.

2. Based on characterization, not tested in production.

2THCLK- 1

-

2

-

3

-

7

-

0

0

-

0.5

ai14992g

Max Unit

-

ns

0

ns

-

ns

2

ns

-

ns

0

ns

-

ns

1

ns

-

ns

-

ns

2

ns

-

ns

130/177

Doc ID 15818 Rev 9

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