STM32F407RG Ver la hoja de datos (PDF) - STMicroelectronics

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componentes Descripción

Fabricante

STM32F407RG

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

STM32F405xx, STM32F407xx

Electrical characteristics

Figure 59. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK)

FSMC_CLK

tw(CLK)

BUSTURN = 0

FSMC_NEx

td(CLKL-NADVL)

FSMC_NADV

FSMC_A[25:16]

Data latency = 0

td(CLKL-NExL)

td(CLKL-NADVH)

td(CLKL-AV)

t d(CLKL-NExH)

td(CLKL-AIV)

td(CLKL-NOEL)

td(CLKL-NOEH)

FSMC_NOE

td(CLKL-ADV)

FSMC_AD[15:0]

td(CLKL-ADIV)

tsu(ADV-CLKH)

AD[15:0]

tsu(NWAITV-CLKH)

th(CLKH-ADV)

tsu(ADV-CLKH)

D1

D2

th(CLKH-ADV)

th(CLKH-NWAITV)

FSMC_NWAIT

(WAITCFG = 1b, WAITPOL + 0b)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

ai14893g

Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2)

Symbol

Parameter

Min

Max

tw(CLK)

FSMC_CLK period

2THCLK

-

td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)

-

0

td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)

2

-

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low

-

2

td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high

2

-

td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25)

-

0

td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25)

0

-

td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low

-

0

td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high

2

-

td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid

-

4.5

td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid

0

-

tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high

6

-

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

DocID022152 Rev 4

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