STM32F405REH6TR Ver la hoja de datos (PDF) - STMicroelectronics
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STM32F405REH6TR Datasheet PDF : 185 Pages
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STM32F405xx, STM32F407xx
Electrical characteristics
Table 82. Synchronous non-multiplexed PSRAM write timings(1)(2)
Symbol
Parameter
tw(CLK)
td(CLKL-NExL)
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2)
td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25)
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high
td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low
td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Min
2THCLK
-
1
-
6
-
6
-
2
-
3
4
0
Max Unit
-
ns
1
ns
-
ns
7
ns
-
ns
0
ns
-
ns
1
ns
-
ns
3
ns
-
ns
-
ns
-
ns
PC Card/CompactFlash controller waveforms and timings
Figure 63 through Figure 68 represent synchronous waveforms, and Table 83 and Table 84
provide the corresponding timings. The results shown in this table are obtained with the
following FSMC configuration:
• COM.FSMC_SetupTime = 0x04;
• COM.FSMC_WaitSetupTime = 0x07;
• COM.FSMC_HoldSetupTime = 0x04;
• COM.FSMC_HiZSetupTime = 0x00;
• ATT.FSMC_SetupTime = 0x04;
• ATT.FSMC_WaitSetupTime = 0x07;
• ATT.FSMC_HoldSetupTime = 0x04;
• ATT.FSMC_HiZSetupTime = 0x00;
• IO.FSMC_SetupTime = 0x04;
• IO.FSMC_WaitSetupTime = 0x07;
• IO.FSMC_HoldSetupTime = 0x04;
• IO.FSMC_HiZSetupTime = 0x00;
• TCLRSetupTime = 0;
• TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
DocID022152 Rev 4
147/185
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