CS61310(2003) Ver la hoja de datos (PDF) - Cirrus Logic

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componentes Descripción

Fabricante

CS61310
(Rev.:2003)

T1 Line Interface Unit

Cirrus Logic 

CS61310

3. ARBITRARY WAVEFORM

GENERATION

In addition to the predefined pulse shapes, the

user can create custom pulse shapes using the

host mode. This flexibility allows the board design-

er to accommodate non-standard cables, EMI fil-

ters, protection circuitry, etc.

The arbitrary pulse shape of mark (a transmitted

“1”) is specified by describing it's pulse shape

across three Unit Intervals (UIs). This allows, for

example, the long haul return-to-zero tail to extend

into the next UI, or two UIs, as is required for iso-

lated pulses.

Each UI is divided into multiple phases, and the us-

ers defines the amplitude of each phase. The

waveform of a space (a transmitted “0”) is fixed at

zero volts. Examples of the phases are shown in

Figure 11. In all cases, to define an arbitrary wave-

form, the user writes to the Waveform Register ei-

ther 36, 39 or 42 times (12, 13 or 14 phases per UI

for three UIs). The phases are written in the order:

UI1/phase1, UI1/phase2, ... , UI1/phase14,

UI2/phase1, ... , UI2/phase14, UI3/phase1, ... ,

UI3/phase14.

For DSX-1 and DS1 applications, the CS61310 di-

vides the 648 ns UI into 13 uniform phases (49.8 ns

each), and will ignore the phase amplitude infor-

mation written for phase 14 of each UI.

When transmitting pulses, the CS61310 will add

the amplitude information from the prior two sym-

bols with the amplitude of the first UI of the current

symbol before outputting a signal on TTIP/TRING.

Therefore, a mark preceded by two spaces will be

output exactly as the mark is programmed. Howev-

er, when one mark is preceded by marks, the first

portion of the last mark may be modified. With AMI

data, where successive pulses have opposite po-

larity, the undershoot tail of one pulse will cause

the rising edge of the next mark to rise more quick-

ly, as shown in Figure 12.

The amplitude of each phase is described by a 7-

bit, 2's complement number, where a positive val-

ue describes pulse amplitude, and a negative val-

ue describes pulse undershoot. The positive full

value is hex 3F. The negative full value is hex 40.

For T1, the typical output voltage is 38 mV/LSB

(peak voltage across the TTIP and TRING out-

puts).

On the secondary of a 1:2 step-up transformer, the

mV/LSB is twice the values stated above. Note that

although the full scale digital input is 3F, it is rec-

ommended that full scale output voltage on the

transformer primary be limited to 2.4 Vpk. At higher

output voltages, the driver may not drive the re-

quested output voltage.

The amplitude information for all phases is written

via the serial-port to Arbitrary Pulse Shape regis-

ters as described in an earlier section. Each phase

DSX -1 (54% duty cycle) Arbitrary W aveform Exam ple

DS-1 (50% duty cycle) Arbitrary W aveform E xam ple

Figure 11. Phase Definition of Arbitrary Waveforms

DS440F1 FEB ‘03

Figure 12. Example of Summing of Waveforms

17

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