JS48F4400PCZ00 Ver la hoja de datos (PDF) - Numonyx -> Micron
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JS48F4400PCZ00 Datasheet PDF : 102 Pages
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Numonyx™ Wireless Flash Memory (W18)
11.3
11.3.1
The 12-V VPP mode enhances programming performance during the short time period
typically found in manufacturing processes; however, it is not intended for extended
use.12 V may be applied to VPP during program and erase operations as specified in
Section 5.0, “Maximum Ratings and Operating Conditions” on page 21. VPP may be
connected to 12 V for a total of tPPH hours maximum. Stressing the device beyond
these limits may cause permanent damage.
Enhanced Factory Program (EFP)
EFP substantially improves device programming performance through a number of
enhancements to the conventional 12 Volt word program algorithm. EFP's more
efficient WSM algorithm eliminates the traditional overhead delays of the conventional
word program mode in both the host programming system and the flash device.
Changes to the conventional word programming flowchart and internal WSM routine
were developed because of today's beat-rate-sensitive manufacturing environments; a
balance between programming speed and cycling performance was attained.
The host programmer writes data to the device and checks the Status Register to
determine when the data has completed programming. This modification essentially
cuts write bus cycles in half. Following each internal program pulse, the WSM
increments the device's address to the next physical location. Now, programming
equipment can sequentially stream program data throughout an entire block without
having to setup and present each new address. In combination, these enhancements
reduce much of the host programmer overhead, enabling more of a data streaming
approach to device programming.
EFP further speeds up programming by performing internal code verification. With this,
PROM programmers can rely on the device to verify that it has been programmed
properly. From the device side, EFP streamlines internal overhead by eliminating the
delays previously associated to switch voltages between programming and verify levels
at each memory-word location.
EFP consists of four phases: setup, program, verify and exit. Refer to Figure 27,
“Enhanced Factory Program Flowchart” on page 64 for a detailed graphical
representation of how to implement EFP.
EFP Requirements and Considerations
Ambient temperature: TA = 25 °C ± 5 °C
EFP Requirements
EFP Considerations
VCC within specified operating range
VPP within specified VPP2 range
Target block unlocked
Block cycling below 100 erase cycles 1
RWW not supported2
EFP programs one block at a time
EFP cannot be suspended
Notes:
1.
Recommended for optimum performance. Some degradation in performance may occur if this limit is
exceeded, but the internal algorithm will continue to work properly.
2.
Code or data cannot be read from another partition during EFP.
November 2007
Order Number: 290701-18
Datasheet
61
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