PC48F4400P0QB0 Ver la hoja de datos (PDF) - Numonyx -> Micron
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PC48F4400P0QB0 Datasheet PDF : 102 Pages
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Numonyx™ Wireless Flash Memory (W18)
14.0 Set Read Configuration Register
The Set Read Configuration Register (RCR) command sets the burst order, frequency
configuration, burst length, and other parameters.
A two-bus cycle command sequence initiates this operation. The Read Configuration
Register data is placed on the lower 16 bits of the address bus (A[15:0]) during both
bus cycles. The Set Read Configuration Register command is written along with the
configuration data (on the address bus). This is followed by a second write that
confirms the operation and again presents the Read Configuration Register data on the
address bus. The Read Configuration Register data is latched on the rising edge of
ADV#, CE#, or WE# (whichever occurs first). This command functions independently of
the applied VPP voltage. After executing this command, the device returns to read-array
mode. The Read Configuration Register’s contents can be examined by writing the Read
Identifier command and then reading location 05h. See Table 30 and Table 31.
Table 30: Read Configuration Register Summary
First Access Latency
Count
Burst Length
RM
R
LC2 LC1 LC0
WT
DOC WC BS
CC
R
R
BW BL2 BL1 BL0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 31: Read Configuration Register Descriptions (Sheet 1 of 2)
Bit
Name
Description1
15
14
13-11
10
9
8
7
6
5
4
RM
Read Mode
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
R
Reserved
LC[2:0]
001 = Reserved
010 = Code 2
First Access Latency Count 011 = Code 3
100 = Code 4
101 = Code 5
111 = Reserved (Default)
WT
WAIT Signal Polarity
0 = WAIT signal is asserted low
1 = WAIT signal is asserted high (Default)
DOC
0 = Hold Data for One Clock
Data Output Configuration 1 = Hold Data for Two Clock (Default)
WC WAIT Configuration
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default)
BS
Burst Sequence
1 = Linear Burst Order (Default)
CC
Clock Configuration
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge (Default)
R
Reserved
R
Reserved
Notes
2
5
6
3
6
6
5
5
Datasheet
78
November 2007
Order Number: 290701-18
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