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PIC12F1822T-I/SL

8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC12F/LF1822/16F/LF1823

23.1.5 CAPTURE DURING SLEEP

Capture mode depends upon the Timer1 module for

proper operation. There are two options for driving the

Timer1 module in Capture mode. It can be driven by the

instruction clock (FOSC/4), or by an external clock source.

When Timer1 is clocked by FOSC/4, Timer1 will not

increment during Sleep. When the device wakes from

Sleep, Timer1 will continue from its previous state.

Capture mode will operate during Sleep when Timer1

is clocked by an external clock source.

TABLE 23-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CCP1CON

P1M<1:0>

DC1B<1:0>

CCP1M<3:0>

CCPR1L Capture/Compare/PWM Register x Low Byte (LSB)

CCPR1H Capture/Compare/PWM Register x High Byte (MSB)

INTCON

GIE

PEIE TMR0IE INTE

IOCIE

TMR0IF INTF

IOCIF

PIE1

PIE2

PIR1

PIR2

T1CON

TMR1GIE

OSFIE

ADIE

C2IE(1)

TMR1GIF

OSFIF

ADIF

C2IF(1)

TMR1CS<1:0>

RCIE

TXIE

C1IE

RCIF

EEIE

TXIF

C1IF

EEIF

T1CKPS<1:0>

SSP1IE

BCL1IE

SSP1IF

BCL1IF

T1OSCEN

CCP1IE

—

CCP1IF

—

T1SYNC

TMR2IE

—

TMR2IF

—

—

TMR1IE

—

TMR1IF

—

TMR1ON

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL

T1GSS<1:0>

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TRISA

—

TRISC(1)

—

—

TRISA5 TRISA4

TRISA3

TRISA2 TRISA1 TRISA0

—

TRISC5 TRISC4

TRISC3

TRISC2 TRISC1 TRISC0

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.

Note 1: PIC16F/LF1823 only.

Register

on Page

221

200

200

89

90

91

92

93

180

181

172

172

121

125

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 201

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