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PIC16LF1937T-E/SP

28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP™ Technology

Microchip Technology 

PIC16F193X/LF193X

TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on all

other

Resets

Bank 5

280h(2) INDF0

281h(2) INDF1

282h(2) PCL

283h(2) STATUS

284h(2) FSR0L

285h(2) FSR0H

286h(2) FSR1L

287h(2) FSR1H

288h(2) BSR

289h(2) WREG

28Ah(1, 2) PCLATH

28Bh(2) INTCON

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

—

—

—

TO

PD

Z

DC

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

—

—

—

BSR4

BSR3

BSR2

BSR1

Working Register

— Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF INTF

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

C

BSR0

IOCIF

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

28Ch

—

Unimplemented

—

—

28Dh

—

Unimplemented

—

—

28Eh

—

Unimplemented

—

—

28Fh

—

Unimplemented

—

—

290h

—

Unimplemented

—

—

291h

CCPR1L

Capture/Compare/PWM Register 1 (LSB)

xxxx xxxx uuuu uuuu

292h

CCPR1H

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx uuuu uuuu

293h

CCP1CON

P1M1

P1M0

DC1B1

DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

294h

PWM1CON P1RSEN P1DC6

P1DC5

P1DC4

P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 0000 0000

295h

CCP1AS

CCP1ASE CCP1AS2 CCP1AS1 CCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000

296h

PSTR1CON

—

—

—

STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001

297h

—

Unimplemented

—

—

298h

CCPR2L

Capture/Compare/PWM Register 2 (LSB)

xxxx xxxx uuuu uuuu

299h

CCPR2H

Capture/Compare/PWM Register 2 (MSB)

xxxx xxxx uuuu uuuu

29Ah

CCP2CON

P2M1

P2M0

DC2B1

DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000

29Bh

PWM2CON P2RSEN P2DC6

P2DC5

P2DC4

P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 0000 0000

29Ch

CCP2AS

CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000

29Dh

PSTR2CON

—

—

—

STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001

29Eh

CCPTMRS0 C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000

29Fh

CCPTMRS1

—

—

—

—

—

—

C5TSEL1 C5TSEL0 ---- --00 ---- --00

Legend:

Note 1:

2:

3:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred

to the upper byte of the program counter.

These registers can be addressed from any bank.

These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.

DS41364B-page 40

Preliminary

© 2009 Microchip Technology Inc.

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