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PIC16C71T-04/SP Datasheet PDF : 176 Pages
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PIC16C71X
8.7 Watchdog Timer (WDT)
Applicable Devices 710 71 711 715
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction. Dur-
ing normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled by clearing configuration bit WDTE
(Section 8.1).
8.7.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT and
the postscaler, if assigned to the WDT, and prevent it
from timing out and generating a device RESET condi-
tion.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
8.7.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
Note:
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
FIGURE 8-20: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
WDT Timer
0
1
M
U
X
Postscaler
8
WDT
Enable Bit
PSA
8 - to - 1 MUX
PS2:PS0
To TMR0 (Figure 6-6)
0
1
MUX
PSA
Note: PSA and PS2:PS0 are bits in the OPTION register.
WDT
Time-out
FIGURE 8-21: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
2007h
Config. bits
(1)
BODEN(1) CP1 CP0 PWRTE(1)
81h,181h OPTION
RBPU INTEDG T0CS T0SE
PSA
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 8-1, Figure 8-2 and Figure 8-3 for operation of these bits.
Bit 2
WDTE
PS2
Bit 1
FOSC1
PS1
Bit 0
FOSC0
PS0
© 1997 Microchip Technology Inc.
DS30272A-page 65
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