STM32F100V6T7BTR Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

STM32F100V6T7BTR

Low & medium-density value line, advanced ARM®-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces

STMicroelectronics 

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

Figure 32. ADC accuracy characteristics

4095

4094

4093

7

6

5

4

3

2

1

[1LSBIDEAL

=VREF+

4096

(or

VDDA depending

4096

on

package)]

EG

(2)

ET

(3)

(1)

EO

EL

ED

1 LSBIDEAL

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

ET=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

EO=Offset Error: deviation between the first actual

transition and the first ideal one.

EG=Gain Error: deviation between the last ideal

transition and the last actual one.

ED=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

EL=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

0

1234567

VSSA

4093 4094 4095 4096

VDDA

ai14395b

Figure 33. Typical connection diagram using the ADC

RAIN(1) AINx

VAIN

Cparasitic

VDD

VT

0.6 V

VT

0.6 V

STM32F10xxx

Sample and hold ADC

converter

RADC(1) 12-bit

converter

IL±1 µA

CADC(1)

ai14139d

1. Refer to Table 42 for the values of RAIN, RADC and CADC.

2.

Cpapdaracsaitpicarceitparnecseen(rtsouthgehlcya7papcFi)ta. nAcheigohf

this, fADC should be reduced.

the PCB

Cparasitic

(dependent on soldering and PCB layout quality) plus the

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 34 or Figure 35,

depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be

ceramic (good quality). They should be placed them as close as possible to the chip.

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