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DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

4.3.1 PAGED MEMORY SCHEME

The dsPIC33EVXXXGM00X/10X family architecture

extends the available DS through a paging scheme,

which allows the available DS to be accessed using

MOV instructions in a linear fashion for pre- and post-

modified Effective Addresses (EAs). The upper half of

the Base Data Space address is used in conjunction

with the Data Space Page registers, the 10-bit Data

Space Read Page register (DSRPAG) or the 9-bit Data

Space Write Page register (DSWPAG), to form an EDS

address, or Program Space Visibility (PSV) address.

The Data Space Page registers are located in the SFR

space. Construction of the EDS address is shown in

Figure 4-9 and Figure 4-10. When DSRPAG<9> = 0

and the base address bit, EA<15> = 1, the

DSRPAG<8:0> bits are concatenated onto EA<14:0> to

form the 24-bit EDS read address. Similarly, when the

base address bit, EA<15> = 1, the DSWPAG<8:0>

bits are concatenated onto EA<14:0> to form the 24-

bit EDS write address.

FIGURE 4-9:

EXTENDED DATA SPACE (EDS) READ ADDRESS GENERATION

16-Bit DS EA

Byte

Select

EA<15> = 0

(DSRPAG = Don’t Care)

Generate

PSV Address

No EDS Access 0

EA<15>

Y DSRPAG<9> 1

= 1?

Select N

DSRPAG

0

DSRPAG<8:0>

9 Bits

EA

EA

15 Bits

24-Bit EDS EA

Note: DS read access when DSRPAG = 0x000 will force an address error trap.

Byte

Select

DS70005144E-page 68

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