PIC18F010T-I/SN データシートの表示（PDF） - Microchip Technology

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PIC18F010T-I/SN

High Performance Microcontrollers

Microchip Technology 

PIC18F010/020

ANDWF

AND WREG with f

Syntax:

[ label ] ANDWF f [ ,d [,a] ]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(WREG) .AND. (f) → dest

Status Affected: N,Z

Encoding:

0001 01da ffff ffff

Description:

The contents of WREG are AND’ed

with register 'f'. If 'd' is 0, the result

is stored in WREG. If 'd' is 1, the

result is stored back in register 'f'

(default). If ’a’ is 0, the Access

Bank will be selected. If ’a’ is 1, the

bank will be selected as per the

BSR value.

Words:

1

Cycles:

1

Q Cycle Activity:

Q1

Decode

Q2

Read

register ’f’

Q3

Process

Data

Q4

Write to

destination

Example:

ANDWF

Before Instruction

WREG = 0x17

REG = 0xC2

N

=?

Z

=?

After Instruction

WREG =

REG =

N

=

Z

=

0x02

0xC2

0

0

REG, W

BC

Branch if Carry

Syntax:

[ label ] BC n

Operands:

-128 ≤ n ≤ 127

Operation:

if carry bit is ’1’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding:

1110 0010 nnnn nnnn

Description:

If the Carry bit is ’1’, then the pro-

gram will branch.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

1

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Q1

Q2

Decode

Read literal

’n’

No

operation

No

operation

If No Jump:

Q1

Q2

Decode

Read literal

’n’

Q3

Process

Data

No

operation

Q3

Process

Data

Q4

Write to PC

No

operation

Q4

No

operation

Example:

HERE

Before Instruction

PC

=

After Instruction

If Carry

=

PC

=

If Carry

=

PC

=

BC 5

address (HERE)

1;

address (HERE+12)

0;

address (HERE+2)

 2001 Microchip Technology Inc.

Preliminary

DS41142A-page 103

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