ST7265x
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
Figure 68. Transfer Sequencing
Master receiver:
S
Address A
Data1
EV1
EV2
A
Data2
EV3
A
.....
EV3
DataN NA
P
EV3
Master transmitter:
S
Address A
Data1
EV1
EV2 EV4
A
Data2
EV4
A
.....
EV4
DataN
A
P
EV4
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV2: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV4: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
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