STPCI2HEYC(2002) データシートの表示（PDF） - STMicroelectronics
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STPCI2HEYC Datasheet PDF : 111 Pages
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DESIGN GUIDELINES
For other implementations like 32-bit SDRAM
devices, refers to the SDRAM controller signal
multiplexing and address mapping described in
the following Table 6-4 and Table 6-5.
Table 6-4. DIMM Pinout
SDRAM Density
Internal Banks
DIMM Pin Number
...
123
126
39
122
16 Mbit
2 Banks
MA[10:0]
-
-
-
BA0 (MA11)
64/128 Mbit
2 Banks
MA[10:0]
MA11
MA12
-
BA0 (MA13)
64/128 Mbit
4 Banks
MA[10:0]
MA11
-
BA1 (MA12)
BA0 (MA13)
STPC I/F
MA[10:0]
CS2# (MA11)
CS3# (MA12)
CS3# (BA1)
BA0
Table 6-5. Address Mapping
Address Mapping: 16 Mbit - 2 internal banks
STPC I/F
BA0
MA10 MA9 MA8
RAS Address A11
A22 A21 A2
CAS Address A11
0
A24 A23
Address Mapping: 64/128 Mbit - 2 internal banks
STPC I/F
BA0 MA12 MA11 MA10 MA9 MA8
RAS Address A11 A24 A23 A22 A21 A20
CAS Address A11 0
0
0
A26 A25
Address Mapping: 64/128 Mbit - 4 internal banks
STPC I/F
BA0 BA1 MA11 MA10 MA9 MA8
RAS Address A11 A12 A24 A23 A22 A21
CAS Address A11 A12 0
0
A26 A25
MA7
A19
A10
MA7
A19
A10
MA7
A20
A10
MA6
A18
A9
MA6
A18
A9
MA6
A19
A9
MA5
A17
A8
MA5
A17
A8
MA5
A18
A8
MA4
A16
A7
MA4
A16
A7
MA4
A17
A7
MA3
A15
A6
MA3
A15
A6
MA3
A16
A6
MA2
A14
A5
MA2
A14
A5
MA2
A15
A5
MA1
A13
A4
MA1
A13
A4
MA1
A14
A4
MA0
A12
A3
MA0
A12
A3
MA0
A13
A3
6.3.4. PCI BUS
The PCI bus is always active and the following
control signals must be pulled-up to 3.3V or 5V
through 2K2 resistors even if this bus is not
connected to an external device: FRAME#,
TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#,
SERR#, PERR#, PCI_REQ#[2:0].
PCI_CLKO must be connected to PCI_CLKI
through a 10 to 33 Ohms resistor. Figure 6-8
shows a typical implementation.
For more information on layout constraints, go to
the place and route recommendations section.
Figure 6-8. Typical PCI clock routing
PCICLKI
0 - 33pF
PCICLKO
0 - 22
10 - 33
PCICLKA
PCICLKB
PCICLKC
Device A
Device B
Device C
Issue 1.0 - July 24, 2002
81/111
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