STPCI2(2002) データシートの表示（PDF） - STMicroelectronics
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STPCI2 Datasheet PDF : 111 Pages
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DESIGN GUIDELINES
6.4. PLACE AND ROUTE
RECOMMENDATIONS
6.4.1. GENERAL RECOMMENDATIONS
All clock signals have to be routed first and
shielded for speeds of 27MHz or higher. The high
speed signals follow the same constraints, as for
the memory and PCI control signals.
Some STPC Interfaces run at high speed and
need to be carefully routed or even shielded like:
The next interfaces to be routed are Memory, PCI,
and Video/graphics.
1) Memory Interface
2) PCI bus
3) Graphics and video interfaces
4) 14 MHz oscillator stage
All the analog noise-sensitive signals have to be
routed in a separate area and hence can be
routed indepedently.
Figure 6-20. Shielding signals
ground ring
shielded signal line
ground pad
ground pad
shielded signal lines
6.4.2. PLL DEFINITION AND IMPLIMENTATION
PLLs are analog cells which supply the internal
STPC Clocks. To get the cleanest clock, the jitter
on the power supply must be reduced as much as
possible. This will result in a more stable system.
Each of the integrated PLL has a dedicated power
pin so a single power plane for all of these PLLs,
or one wire for each, or any solution in between
which help the layout of the board can be used.
Powering these pins with one Ferrite +
capacitances is enough. We recommend at least
2 capacitances: one 'big' (few uF) for power
storage, and one or 2 smalls (100nF + 1nF) for
noise filtering.
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Issue 1.0 - July 24, 2002
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