ELECTRICAL SPECIFICATIONS
The Table 4-12 below refers to Vh, Va, Vs which
are the register value for Setup time, Active Time
and Hold time, as described in the Programming
Manual.
Table 4-12. Local Bus cycle lenght
Cycle
Memory (FCSx#)
Peripheral (IOCSx#)
Tsetup
4 + Vh
8 + Vh
Tactive
2 + Va
3 + Va
Thold
4 + Vs
4 + Vs
Tend
4
4
Unit
HCLK
HCLK
Name
Table 4-13. Local Bus Interface AC Timing
Parameters
Min
HCLK to PA bus
-
HCLK to PD bus
-
HCLK to FCS#[1:0]
-
HCLK to IOCS#[3:0]
-
HCLK to PWR#[1:0]
-
HCLK to PRD#[1:0]
-
PD[15:0] Input setup to HCLK
-
PD[15:0] Input hold to HCLK
2
PRDY Input setup to HCLK
-
PRDY Input hold to HCLK
2
Max
Units
15
nS
15
nS
15
nS
15
nS
15
nS
15
nS
4
nS
-
nS
4
nS
-
nS
50/87
Release 1.3 - January 29, 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.