STPCE1EDBI データシートの表示（PDF） - STMicroelectronics
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STPCE1EDBI Datasheet PDF : 87 Pages
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DESIGN GUIDELINES
6.3.4. PCI BUS
The PCI bus is always active and the following
control signals must be pulled-up to 3.3V or 5V
through 2K2 resistors even if this bus is not
connected to an external device: FRAME#,
TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#,
SERR#, PCI_REQ#[2:0].
PCI_CLKO must be connected to PCI_CLKI
through a 10 to 33 Ohms resistor. Figure 6-7
shows a typical implementation.
For more information on layout constraints, go to
the place and route recommendations section.
Figure 6-7. Typical PCI clock routing
PCICLKI
0 - 33pF
PCICLKO
0 - 22
10 - 33
PCICLKA
PCICLKB
PCICLKC
Device A
Device B
Device C
In the case of higher clock load it is recommended
to use a zero-delay clock buffer as described in
Figure 6-8. This approach is also recommended
when implementing the delay on PCICLKI
according to the PCI section of the Electrical
Specifications chapter.
Figure 6-8. PCI clock routing with zero-delay clock buffer
PCICLKI
PCICLKI
PCICLKO
PLL
CY2305
Device A
Device B
Device C
Device D
Implementation 1
PCICLKO
PLL
CY2305
Device A
Device B
Device C
Device D
Implementation 2
Release 1.3 - January 29, 2002
65/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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