CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

17.1 FPA Functional Blocks

FPA consists of five main functional blocks described in the following sections.

q Coprocessor interface

q Instruction issuer

q Load-store unit

q Register bank

q ALU

17.1.1 Coprocessor Interface

This block is responsible for arbitrating instructions with the CPU and relating to the load-store unit when

to go ahead with data transfers.

Like ARM integer instructions, all ARM floating-point instructions are conditional, obviating the need for

branches for many common constructs. If a failed condition causes an instruction already issued to the

load-store unit or ALU to be skipped, that instruction is cancelled and any results calculated thus far are

discarded.

The same mechanism is used to cancel prefetched instructions if a branch is taken or if the ARM CPU

gets interrupted before an FPA instruction has been arbitrated.

17.1.2 Instruction Issuer

The instruction issuer is responsible for examining the incoming instruction stream and deciding if any

instructions are candidates for issuing to either the load-store unit or the ALU.

Instructions can be selected from the fetch, decode or execute stages of the ARM pipeline follower. Data

anti-dependency hazards (write-after-write and write-after-read) are dealt with by this unit by preventing

issuance until the hazard is cleared.

Instructions are issued strictly in order and only one can be issued per cycle.

17.1.3 Load-Store Unit

The load-store unit does the formatting and conversion necessary when moving data between the 32-bit

ARM data bus and the 81-bit internal register format. It is also responsible for checking all input operands

and flagging any that are not normalized numbers or zero.

Most subsequent operations on flagged data cause the instruction to be passed to software which will

then emulate the instruction. All internal operations are performed to the internal 81-bit format.

17.1.4 Register Bank

The register bank contains eight 81-bit dual read-access, dual write-access registers.

Data dependency hazards (read-after-write) are handled by the register control logic; read requests from

either unit are stalled until the hazard is cleared.

There is also a 33-bit temporary register, used by the FIX, FLT, and compare instructions to transfer inter-

mediate results between the load-store unit and the ALU.

June 1997

ADVANCE DATA BOOK v2.0

FPA COPROCESSOR MACROCELL

157

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