CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

List of System IDs

The following system IDs are defined:

Floating-point Emulator

01 (HEX) (Software only)

FPA System

81 (HEX)

The following system IDs are also defined for backwards compatibility:

00(HEX) for pre-FPA software systems

80(HEX) for pre-FPA hardware systems

18.4.2 Exception Trap Enable Byte

31

23

21 20 19 18 17 16

0

Reserved IXE UFEOFEDZE IOE

Each bit of the exception trap enable byte corresponds to one type of floating-point exception. The excep-

tion types (IX,UF,OF,DZ,IO) are described below.

A bit in the cumulative exception flags byte is set as a result of executing a floating-point instruction only

if the corresponding bit is not set in the exception trap enable byte; if the corresponding bit in the exception

trap enable byte is set, an exception trap will be taken instead of setting the exception flag. The trap han-

dler code can then set the relevant cumulative exception bit if desired.

Normally, reserved FPSR bits should not be altered by user code. However, they can be initialized to zero.

18.4.3 System Control Byte

15

13 12 11 10 9 8

Reserved AC EP SO NE ND

These control bits determine which features of the floating-point system are in use. Because these control

bits are in the FPSR, their state will be preserved across context switches, allowing different processes

to use different features if necessary. The following five control bits are defined for the FPA system:

Bit 8

Bit 9

ND - No Denormalized Numbers Bit

If this bit is set, the software forces all denormalized numbers to zero to reduce

lengthy execution times when dealing with denormalized numbers. (Also

known as abrupt underflow or flush to zero.) This mode is not IEEE-compatible

but may be required by some programs for performance reasons. If this bit is

clear, then denormalized numbers will be handled in the normal IEEE-

conformant way.

NE - NaN Exception Bit

When this bit is clear, extended format is regarded as an internal format for

conversions of signalling NaNs: only conversions between single and double-

precision will produce an invalid operation exception because of a signalling

NaN operand. This is required for compatibility with old programs which use

STFE and LDFE to preserve register contents. When the NE bit is set, all

conversions between single, double and extended precision will produce an

invalid operation exception if the operand is a signalling NaN.

June 1997

ADVANCE DATA BOOK v2.0

FLOATING-POINT COPROCESSOR PROGRAMMER’S

MODEL

165

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