CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

As another example, consider a ROM interface where the non-sequential access time is programmed at

7 cycles and the sequential access is programmed to 4 cycles using 16-bit-wide ROM. The total latency is:

3.5 + 2 + 14 + 8 + 8 + 8 + 5.5 = 49 MEMCLK cycles

Equation 20-3

At 32 MHz this corresponds to 1.5 µs.

190

BUS INTERFACE

ADVANCE DATA BOOK v2.0

June 1997

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