CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Immediately after the table, the CL-PS7500FE is in 32-bit mode. The eight locations, from address 20 to

3C, must be programmed with eight half-words in the lower sixteen bits of each location. These form the

four required 32-bit instructions when read in pairs by the CL-PS7500FE. The upper 16 bits of each loca-

tion are ignored by the CL-PS7500FE while still in 16-bit mode.

The four instructions program ROMCR0 into 32-bit mode and cause program execution to jump back to

the reset vector at physical address zero. This now be executes correctly. The MOV PC – #0 instruction,

that actually causes execution to jump back to zero, must be prefetched in 16-bit mode even though it

occurs after the ROMCR0 is reprogrammed. Table A-2 shows the data required at memory locations 0x20

to 0x3C to implement this scheme.

Table A-2. Instructions for Programming the ROM Register

Data

Address Instruction

0x0000B632

0x0000E3A0

0x00000000

0x0000E3A0

0x00000080

0x0000E5CB

0x0000F000

0x0000E3A0

20

24

MOV R11, 0x03200000

28

2C

MOV R0, #&0

30

34

STRB R0, [R11,0x80]

38

3C

MOV PC, #0

Notes

Point at register base.

32b, slow, 218.75 µs, no burst.

Program ROMCR0 and switch mode.

Jump to zero.

The boot code above is a general example to set the ROM interface to use the slowest access timing This

ensures it works with all systems. To speed execution, program the ROM control registers with the fastest

parameters of the interface. On power up, the default state of the CLKCTL register is for the CPUCLK,

MEMCLK, and I_OCLK external clock inputs to be divided by 2. If appropriate, program these clocks to

divide-by-1. This also speeds execution.

3. Other Methods

The above method is an example of how the CL-PS7500FE can be booted from a system using 32-bit-

wide ROM. There are other methods to do this that may be more appropriate for the required application.

The main advantage of the above method is that it allows the exception vector table to reside at physical

address 0. If this is not a requirement the instructions that reprogram ROMCR0 can reside from location

0 up, and the vector table can be mapped into DRAM by the operating system software.

228

June 1997

ADVANCE DATA BOOK v2.0

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