CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Appendix F

F.CL-PS7500FE Test Modes

1. Introduction

The CL-PS7500FE has a pin, nTEST, combined with the nINT8, nINT3, and nINT6 pins to set the device

into various test modes. Most of these are intended for use only during production testing to allow the indi-

vidual macrocells within the CL-PS7500FE to be tested directly from the external pins using a MUX-iso-

lation scheme.

2. Test Modes Description

When the nTEST pin is high, the CL-PS7500FE is in normal operating mode irrespective of the states of

nINT8, nINT3, and nINT6. However, when nTEST is set low, the chip is set into one of five possible test

modes dependent on the state of the three inputs nINT8, nINT3, and nINT6. Four of these test modes are

reserved for use on the tester.

However there is one test mode that, when selected, causes all the CL-PS7500FE outputs to be tristate.

This test mode is accessed by setting nTEST = 0, nINT8 = 0, nINT3 = 1, and nINT6 = 1.

IMPORTANT: Select no other combinations.

June 1997

ADVANCE DATA BOOK v2.0

241

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