Z8018220ASC データシートの表示（PDF） - Zilog

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Z8018220ASC

ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog 

Zilog

PRELIMINARY

SYSTEM CONTROL REGISTERS

IL

Addr 33H

Bit

IL7 IL6 IL5 -

-

-

-

-

Upon Reset

00000000

R/W

R/W R/W R/W

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

Interrupt Vector Low

Figure 46. Interrupt Vector Low Register

ITC

Bit

TRAP UFO -

-

Upon Reset

0

0

1

1

R/W

R/W R

Addr 34H

- ITE2 ITE1 ITE0

1001

R/W R/W R/W

Figure 47. INT/TRAP Control Register

/INT Enable 2, 1, 0

Undefined Fetch Object

TRAP

RCR

Addr 36H

Bit

REFE REFW -

-

-

- CYC1 CYC0

Upon Reset

1

1

1

1

1

1

0

0

R/W

R/W R/W

R/W R/W

Cycle Select

Refresh Wait State

Refresh Enable

CYC1, 0

00

01

10

11

Interval of Refresh Cycle

10 states

20 states

40 states

80 states

Figure 48. Refresh Control Register

DS971820600

PS009801-0301

3-43

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