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STM32F103VC データシートの表示(PDF) - STMicroelectronics

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STM32F103VC Datasheet PDF : 123 Pages
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STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
5.3.19 DAC electrical specifications
Table 62. DAC characteristics
Symbol
Parameter
Min Typ
Max
Unit
Comments
VDDA
Analog supply voltage
2.4
3.6
V
VREF+
VSSA
RLOAD(1)
Reference supply voltage 2.4
Ground
0
Resistive load with buffer ON 5
RO(1)
Impedance output with buffer
OFF
3.6
V VREF+ must always be below VDDA
0
V
k
When the buffer is OFF, the Minimum
15
k
resistive load between DAC_OUT
and VSS to have a 1% accuracy is
1.5 M
CLOAD(1) Capacitive load
Maximum capacitive load at
50
pF DAC_OUT pin (when the buffer is
ON).
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer ON
0.2
DAC_OUT Higher DAC_OUT voltage
max(1)
with buffer ON
V
VDDA – 0.2 V
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V
and (0x155) and (0xEAB) at VREF+ =
2.4 V
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer OFF
DAC_OUT Higher DAC_OUT voltage
max(1)
with buffer OFF
0.5
mV
It gives the maximum output
VREF+ – 1LSB V
excursion of the DAC.
IDDVREF+
DAC DC current
consumption in quiescent
mode (Standby mode)
With no load, worst code (0xF1C) at
220
µA VREF+ = 3.6 V in terms of DC
consumption on the inputs
DAC DC current
IDDA
consumption in quiescent
mode (Standby mode)
380
µA
With no load, middle code (0x800) on
the inputs
With no load, worst code (0xF1C) at
480
µA VREF+ = 3.6 V in terms of DC
consumption on the inputs
DNL(2)
Differential non linearity
Difference between two
consecutive code-1LSB)
INL(2)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
±0.5
±2
±1
±4
LSB
Given for the DAC in 10-bit
configuration
LSB
Given for the DAC in 12-bit
configuration
LSB
Given for the DAC in 10-bit
configuration
LSB
Given for the DAC in 12-bit
configuration
Doc ID 14611 Rev 7
103/123

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