GL811USB データシートの表示（PDF） - Genesys Logic

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GL811USB

USB 2.0 to ATA / ATAPI Bridge Controller

Genesys Logic 

GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller

6.4.1 Register transfers

ADDR valid

(Note1)

t1

DIOR_/DIOW_

WRITE IODD(7:0)

(Note2)

Read IODD(7:0)

(Note2)

IORDY (Note3.1)

IORDY (Note3.2)

IORDY (Note3.3)

t0

t2

t9

t2i

t3

t4

t5

t6

t6z

tA

tC

tRD

tB

tC

Notes:

1.Device address consists of signals CS0_, CS1_ and DA(2:0).

2.Data consists of IODD(7:0).

3.The negation of IORDY by the device is used to extend the register transfer cycle. The

determination of whether the cycle is to be extended is made by the host after tA from the

assertion of DIOR_ or DIOW_. The assertion and negation of IORDY are described as

following:

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