FDC37B78X データシートの表示（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

GENERAL PURPOSE I/O

The FDC37B78x provides a set of flexible

Input/Output control functions to the system

designer through the 21 dedicated

independently programmable General Purpose

I/O pins (GPIO). The GPIO pins can perform

simple I/O or can be individually configured to

provide predefined alternate functions. VBAT

Power-On-Reset configures all GPIO pins as

non-inverting inputs.

Description

Each GPIO port requires a 1-bit data register

and an 8-bit configuration control register. The

data register for each GPIO port is represented

as a bit in one of three 8-bit GPIO DATA

Registers, GP1, GP5, and GP6. All of the GPIO

registers are located in Logical Device Block No.

8 in the FDC37B78x device configuration space.

The GPIO DATA Registers are also optionally

available at different addresses when the

FDC37B78x is in the Run state. The GPIO

ports with their alternate functions and

configuration state register addresses are listed

in. Note: three bits 5-7 of GP5 are not

implemented.

TABLE 52 - GENERAL PURPOSE I/O PORT ASSIGNMENTS

PIN NO.

QFP

DEFAULT

FUNCTION

ALT.

FUNC. 1

ALT.

FUNC. 2

ALT.

FUNC. 3

DATA

REGISTER

4 (HEX)

DATA

REGISTER

BIT NO.

CONFIG.

REGISTER4

(HEX)

77

GPIO

nSMI

-

-

GP1

0

78

GPIO

nRING

EETI1

-

(CRF6)

1

79

GPIO

WDT

P17

EETI1

2

CRE0

CRE1

CRE2

80

GPIO

LED

-

-

3

CRE3

81

GPIO

IRRX2

-

-

4

CRE4

82

GPIO

IRTX2

-

-

5

CRE5

4

GPIO

nMTR1 -

-

6

CRE6

6

GPIO

nDS1

-

-

7

CRE7

39

PCI_CLK

IRQ14

GPIO

-

GP5

0

2

DRVDEN15 GPIO

IRQ8

nSMI

(CRF9)

2

91

nROMCS2

IRQ11

GPIO

EETI1

3

92

nROMOE2

IRQ12

GPIO

EETI1

4

83

RD02,3

IRQ1

GPIO

nSMI

GP6

0

84

RD12,3

IRQ3

GPIO

LED

(CRFA)

1

85

RD22,3

IRQ4

GPIO

nRING

2

86

RD32,3

IRQ5

GPIO

WDT

3

87

RD42,3

IRQ6

GPIO

P17

4

88

RD52,3

IRQ7

GPIO

-

5

89

RD62,3

IRQ8

GPIO

-

6

90

RD72,3

IRQ10

GPIO

-

7

CRC8

CRCA

CRCB

CRCC

CRD0

CRD1

CRD2

CRD3

CRD4

CRD5

CRD6

CRD7

Note 1. Refer to the section on Either Edge Triggered Interrupt Inputs.

Note 2. At power-up, RD0-7, nROMCS and nROMOE function as the XD Bus. To use RD0-7 for

alternate functions, nROMCS must stay high until those pins are finished being

programmed.

Note 3. These pins cannot be programmed as open drain pins in their original function.

Note 4. The GPIO Data and Configuration Registers are located in Logical Device 8.

Note 5: This pin defaults to its GPIO function. See Configuration Registers.

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