PIC16CE624T-04E/SW301 データシートの表示（PDF） - Microchip Technology
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PIC16CE624T-04E/SW301 Datasheet PDF : 108 Pages
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PIC16CE62X
9.0 VOLTAGE REFERENCE
MODULE
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Figure 9-1. The block diagram is
given in Figure 9-2.
9.1 Configuring the Voltage Reference
The Voltage Reference can output 16 distinct voltage
levels for each range.
The equations used to calculate the output of the
Voltage Reference are as follows:
if VRR = 1: VREF = (VR<3:0>/24) x VDD
if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD
The setting time of the Voltage Reference must be
considered when changing the VREF output
(Table 13-2). Example 9-1 shows an example of how to
configure the Voltage Reference for an output voltage
of 1.25V with VDD = 5.0V.
FIGURE 9-1: VRCON REGISTER(ADDRESS 9Fh)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
VREN
VROE
VRR
—
VR3
VR2
VR1
bit7
bit 7:
VREN: VREF Enable
1 = VREF circuit powered on
0 = VREF circuit powered down, no IDD drain
bit 6:
VROE: VREF Output Enable
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5:
VRR: VREF Range selection
1 = Low Range
0 = High Range
bit 4: Unimplemented: Read as '0'
bit 3-0: VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15
when VRR = 1: VREF = (VR<3:0>/ 24) * VDD
when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
R/W-0
VR0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
FIGURE 9-2: VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREN
8R
R
R
R
R
8R
VRR
VREF
Note: R is defined in Table 13-3.
© 1998 Microchip Technology Inc.
16-1 Analog Mux
Preliminary
VR3
(From VRCON<3:0>)
VR0
DS40182A-page 47
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