PSD913G3V-C-90JI データシートの表示（PDF） - STMicroelectronics

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PSD913G3V-C-90JI

Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs

STMicroelectronics 

PSD9XX Family

Preliminary Information

Microcontroller Interface – PSD9XX AC/DC Parameters

(5V ± 10% Versions)

Power Down Timing (5 V ± 10%)

-70

-90

-15

Symbol

Parameter

t LVDV

ALE Access Time from

Power Down

t CLWH

Maximum Delay from APD

Enable to Internal PDN

Valid Signal

NOTE: 1. tCLCL is the CLKIN clock period.

Conditions

Min Max Min Max Min Max Unit

80

90

150 ns

Using

CLKIN Input

15 * tCLCL (µs) (Note 1)

µs

Vstbyon Timing (5 V ± 10%)

Symbol

Parameter

t BVBH

Vstby Detection to Vstbyon Output High

t BXBL

Vstby Off Detection to Vstbyon

Output Low

NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.

Conditions

(Note 1)

(Note 1)

Min

Typ

Max Unit

20

µs

20

µs

Reset Pin Timing (5 V ± 10%)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

t NLNH

Warm RESET Active Low Time (Note 1)

150

t OPR

RESET High to Operational Device

tNLNH-PO Power On Reset Active Low Time

1

Warm Reset, will abort and reset Flash

tNLNH-A programming/erase cycles to Read mode.

25

(Note 2)

NOTE: 1. RESET will not reset Flash programming/erase cycles.

2. RESET will abort Flash programming or erase cycle. For PSD934F2 and PSD954F2 only.

ns

120

ns

ms

µs

70

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