PSD935F3-90UI データシートの表示（PDF） - STMicroelectronics
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PSD935F3-90UI Datasheet PDF : 91 Pages
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PSD9XX Family
PSD935G2
Microcontroller Interface – PSD935G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Write Timing (3.0 V to 3.6 V Versions)
Symbol
t LVLX
t AVLX
t LXAX
t AVWL
t SLWL
t DVWH
t WHDX
t WLWH
t WHAX1
t WHAX2
t WHPV
t AVPV
Parameter
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Leading
Edge of WR
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
WR Pulse Width
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Input Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
Address Input Valid to Address
Output Delay
Conditions
(Note 1)
(Note 1)
(Notes 1 and 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Notes 3 and 4)
(Note 3)
(Note 2)
-90
-12
Min Max Min Max Unit
22
24
7
9
ns
8
10
ns
15
18
ns
15
18
ns
40
45
ns
5
8
ns
40
45
ns
8
10
ns
0
0
ns
33
33 ns
30
35 ns
NOTES: 1. Any input used to select an internal PSD935G2 function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, DS signals.
4. tWHAX2 is Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
PLD Combinatorial Timing (5 V ± 10%)
Symbol
t PD
Parameter
PLD Input Pin/Feedback to
PLD Combinatorial Output
tARD PLD Array Delay
Conditions
-90
Min Max
-12
Min Max
TURBO
OFF
Slew
Rate
(Note 1) Unit
38
43 Add 20 Sub 6 ns
23
27
ns
NOTE: 1. Fast Slew Rate output available on Port C and F.
76
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