ST72E121J4D0 データシートの表示（PDF） - STMicroelectronics

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ST72E121J4D0

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS

STMicroelectronics 

ST72E121 ST72T121

SERIAL PERIPHERAL INTERFACE (Cont’d)

4.5.5 Low Power Modes

Mode

WAIT

HALT

Description

No effect on SPI.

SPI interrupt events cause the device to exit from WAIT mode.

SPI registers are frozen.

In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with

“exit from HALT mode” capability.

4.5.6 Interrupts

Interrupt Event

SPI End of Transfer Event

Master Mode Fault Event

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the I-bit in the CC reg-

ister is reset (RIM instruction).

Event

Flag

SPIF

MODF

Enable

Control

Bit

SPIE

Exit

from

Wait

Yes

Yes

Exit

from

Halt

No

No

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