Z80230 データシートの表示（PDF） - Zilog

部品番号

コンポーネント説明

メーカー

Z80230

Zilog SCC Serial Communication Controller

Zilog 

Application Note

Boost Your System Performance Using The Zilog ESCC™

MODIFIED WRITE TIMING

In the SCC write cycle, the SCC assumes the data is valid In the ESCC, write cycle timing has been modified so that

1 when /WR is asserted (Figure 15). This assumption is not data becomes valid a short time after write (approx. 20 ns).

valid for some CPUs, e.g., the Intel 80X86. The /WR signal Therefore, if the data pins from the Intel CPU are

from this CPU needs to delay for one more clock to initiate connected directly to the ESCC, no additional logic is

the write cycle. Additional hardware is required.

required.

/WR

SCC

ESCC

Databus Valid

SCC Spec:

WR Falling

29

Databus Va

Minimum

ESCC Spec:

29

Databus Valid to WR Falling

Databus Valid

Databus latched after falling edge of WR saves external logic required

to delay WR until databus is valid. Typically needed with Intel CPUs.

Figure 15. Modified Write Timing

UM010901-0601

6-129

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