PIC16LF1826-I/SS データシートの表示（PDF） - Microchip Technology
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PIC16LF1826-I/SS
Microchip Technology
PIC16LF1826-I/SS Datasheet PDF : 406 Pages
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PIC16F/LF1826/27
TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 1
080h(2) INDF0
081h(2) INDF1
082h(2)
083h(2)
084h(2)
085h(2)
086h(2)
087h(2)
088h(2)
089h(2)
08Ah(2)
08Bh(2)
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
Working Register
—
Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
DC
BSR1
INTF
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
BSR0
IOCIF
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
08Ch TRISA
TRISA7
TRISA6
TRISA5
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
08Dh TRISB
TRISB7
TRISB6
TRISB5
TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
08Eh —
Unimplemented
—
—
08Fh
—
Unimplemented
—
—
090h
—
Unimplemented
—
—
091h
092h
093h
094h
PIE1
PIE2
PIE3(1)
PIE4(1)
TMR1GIE
OSFIE
—
—
ADIE
C2IE
—
—
RCIE
C1IE
CCP4IE
—
TXIE
EEIE
CCP3IE
—
SSP1IE
BCL1IE
TMR6IE
—
CCP1IE
—
—
—
TMR2IE
—
TMR4IE
BCL2IE
TMR1IE 0000 0000 0000 0000
CCP2IE(1) 0000 0--0 0000 0--0
—
--00 0-0- --00 0-0-
SSP2IE ---- --00 ---- --00
095h
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE
PSA
PS2
PS1
PS0 1111 1111 1111 1111
096h
PCON
STKOVF STKUNF
—
—
RMCLR
RI
POR
BOR 00-- 11qq qq-- qquu
097h
WDTCON
—
—
WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110
098h
OSCTUNE
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0 --00 0000 --00 0000
099h
OSCCON
SPLLEN
IRCF3
IRCF2
IRCF1
IRCF0
—
SCS1
SCS0 0011 1-00 0011 1-00
09Ah OSCSTAT
T1OSCR
PLLR
OSTS
HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q
09Bh ADRESL
A/D Result Register Low
xxxx xxxx uuuu uuuu
09Ch ADRESH
A/D Result Register High
xxxx xxxx uuuu uuuu
09Dh ADCON0
—
CHS4
CHS3
CHS2
CHS1
CHS0 GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1
ADFM
ADCS2
ADCS1
ADCS0
—
ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000
09Fh
—
Unimplemented
—
—
Legend:
Note 1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
PIC16F/LF1827 only.
These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 31
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