OR2T15B7BA352-DB データシートの表示（PDF） - Lattice Semiconductor
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OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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ORCA Series 2 FPGAs
Data Sheet
November 2006
Timing Characteristics (continued)
Table 53A. OR2CxxA/OR2TxxA Slave Parallel Configuration Mode Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
CS0, CS1, WR Setup Time
S CS0, CS1, WR Hold Time
D[7:0] Setup Time
D[7:0] Hold Time
E CCLK High Time
CCLK Low Time
IC CCLK Frequency
Symbol
Min
TS1
60
TH1
20
TS2
20
TH2
0
TCH
50
TCL
50
FC
—
D Note: Daisy chaining of FPGAs is not supported in this mode.
Max
—
—
—
—
—
—
10
Unit
ns
ns
ns
ns
ns
ns
MHz
V Table 53B. OR2TxxB Slave Parallel Configuration Mode Timing Characteristics
E OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
E Parameter
U CS0, CS1, WR Setup Time
CS0, CS1, WR Hold Time
D IN D[7:0] Setup Time
D[7:0] Hold Time
CCLK High Time
T T CCLK Low Time
CCLK Frequency
Symbol
TS1
TH1
TS2
TH2
TCH
TCL
FC
Min
—
15
15
0
12.5
12.5
—
Max
—
—
—
—
—
—
40
Unit
—
ns
ns
ns
ns
ns
MHz
C N Note: Daisy chaining of FPGAs is not supported in this mode.
E CS0
EL CO CS1
S DIS WR
TS1
TH1
CCLK
TS2
TH2
D[7:0]
5-2848(F)
Figure 71. Slave Parallel Configuration Mode Timing Diagram
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