STM32F205VE データシートの表示（PDF） - STMicroelectronics
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STM32F205VE Datasheet PDF : 177 Pages
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STM32F20xxx
Electrical characteristics
I2S - SPI interface characteristics
Unless otherwise specified, the parameters given in Table 52 for SPI or in Table 53 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 12.
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 52. SPI characteristics
Symbol
Parameter
Conditions
Min
Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
SPI1 master/slave mode
SPI2/SPI3 master/slave mode
-
30
MHz
-
15
tr(SCL)
tf(SCL)
SPI clock rise and fall Capacitive load: C = 30 pF,
time
fPCLK = 30 MHz
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
tsu(NSS)(1)
th(NSS)(1)
tw(SCLH)(1)
tw(SCLL)(1)
NSS setup time
Slave mode
NSS hold time
Slave mode
SCK high and low time
Master mode, fPCLK = 30 MHz,
presc = 2
tsu(MI) (1)
tsu(SI)(1)
Master mode
Data input setup time
Slave mode
-
8
ns
30
70
%
4tPCLK
-
2tPCLK
-
tPCLK-3 tPCLK+3
5
-
5
-
th(MI) (1)
th(SI)(1)
Data input hold time
ta(SO)(1)(2)
Data output access
time
Master mode
Slave mode
Slave mode, fPCLK = 30 MHz
5
-
4
-
ns
0
3tPCLK
tdis(SO)(1)(3)
Data output disable
time
Slave mode
2
10
tv(SO) (1) Data output valid time Slave mode (after enable edge)
-
25
tv(MO)(1) Data output valid time Master mode (after enable edge)
-
5
th(SO)(1)
Slave mode (after enable edge)
15
-
Data output hold time
th(MO)(1)
Master mode (after enable edge)
2
-
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Doc ID 15818 Rev 9
105/177
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