STM32F405REH6TR データシートの表示（PDF） - STMicroelectronics

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STM32F405REH6TR

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

STM32F405xx, STM32F407xx

Electrical characteristics

Table 80. Synchronous multiplexed PSRAM write timings(1)(2)

td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25)

8

-

ns

td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low

-

0.5

ns

td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high

0

-

ns

td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid

0

-

ns

td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low

-

3

ns

td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high

0

-

ns

tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high

4

-

ns

th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high

0

-

ns

1. CL = 30 pF.

2. Based on characterization, not tested in production.

Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK)

FSMC_CLK

tw(CLK)

BUSTURN = 0

td(CLKL-NExL)

FSMC_NEx

Data latency = 0

td(CLKL-NExH)

td(CLKL-NADVL)

FSMC_NADV

td(CLKL-NADVH)

FSMC_A[25:0]

td(CLKL-AV)

td(CLKL-AIV)

FSMC_NOE

FSMC_D[15:0]

FSMC_NWAIT

(WAITCFG = 1b, WAITPOL + 0b)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

td(CLKL-NOEL)

td(CLKL-NOEH)

tsu(DV-CLKH)

tsu(NWAITV-CLKH)

th(CLKH-DV)

tsu(DV-CLKH)

D1

D2

th(CLKH-DV)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

t h(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

ai14894f

Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)

Symbol

Parameter

Min

Max Unit

tw(CLK)

td(CLKL-NExL)

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x=0..2)

2THCLK –0.5

-

ns

-

0.5

ns

DocID022152 Rev 4

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