STM32F405OGY7TR データシートの表示（PDF） - STMicroelectronics

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STM32F405OGY7TR

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

Revision history

STM32F405xx, STM32F407xx

Table 98. Document revision history (continued)

Date

Revision

Changes

04-Jun-2013

Updated Table 64: Dynamic characteristics: Ehternet MAC signals for

SMI.

Updated Table 66: Dynamic characteristics: Ethernet MAC signals for

MII.

Updated Table 79: Synchronous multiplexed NOR/PSRAM read

timings.

Updated Table 80: Synchronous multiplexed PSRAM write timings.

4

(continued)

Updated Table 81: Synchronous non-multiplexed NOR/PSRAM read

timings.

Updated Table 82: Synchronous non-multiplexed PSRAM write

timings.

Updated Section 5.3.26: Camera interface (DCMI) timing specifications

including Table 87: DCMI characteristics and addition of Figure 73:

DCMI timing diagram.

Updated Section 5.3.27: SD/SDIO MMC card host interface (SDIO)

characteristics including Table 88.

Updated Chapter Figure 9.

184/185

DocID022152 Rev 4

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