STM32F405RET7 データシートの表示（PDF） - STMicroelectronics
部品番号
コンポーネント説明
メーカー
STM32F405RET7 Datasheet PDF : 185 Pages
| |||
Description
STM32F405xx, STM32F407xx
2.2
Device overview
Figure 5. STM32F40x block diagram
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
TRACECLK
TRACED[3:0]
MII or RMII as AF
MDIO as AF
DP, DM
ULPI:CK, D[7:0], DIR, STP, NXT
ID, VBUS, SOF
CCM data RAM 64 KB
JTAG & SW
ETM
MPU
NVIC
ARM Cortex-M4
168 MHz
FPU
D-BUS
I-BUS
S-BUS
Ethernet MAC DMA/
10/100
FIFO
USB
OTG HS
DMA/
FIFO
DMA2
DMA1
8 Streams
FIFO
8 Streams
FIFO
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
PH[15:0]
PI[11:0]
GPIO PORT A
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
GPIO PORT F
GPIO PORT G
GPIO PORT H
GPIO PORT I
140 AF
D[7:0]
CMD, CK as AF
4 compl. channels (TIM1_CH1[1:4]N,
4 channels (TIM1_CH1[1:4]ETR,
BKIN as AF
4 compl. channels (TIM1_CH1[1:4]N,
4 channels (TIM1_CH1[1:4]ETR,
BKIN as AF
2 channels as AF
1 channel as AF
1 channel as AF
RX, TX, CK,
CTS, RTS as AF
RX, TX, CK,
CTS, RTS as AF
MOSI, MISO,
SCK, NSS as AF
VDDREF_ADC
8 analog inputs common
to the 3 ADCs
8 analog inputs common
to the ADC1 & 2
8 analog inputs for ADC3
EXT IT. WKUP
SDIO / MMC
TIM1 / PWM 16b
TIM8 / PWM 16b
TIM9
16b
TIM10 16b
TIM11
16b
smcard
irDA
USART1
smcard
irDA
USART6
SPI1
@VDDA
Temperature sensor
ADC1
ADC2
IF
ADC3
External memory
controller (FSMC)
AHB3 SRAM, PSRAM, NOR Flash,
PC Card (ATA), NAND Flash
Flash
up to
1 MB
SRAM 112 KB
SRAM 16 KB
AHB2 168 MHz
AHB1 168 MHz
@VDDA
RC HS
RC L S
P L L1&2
Reset &
M AclNockA G T
control
DMA2
DMA1
AHB/APB2 AHB/APB1
WWDG
TIM6
TIM7
@VDDA
DAC1
DAC2
16b
16b
ITF
RNG
Camera
interface
USB
OTG FS
VDD
POR
reset
Int
Power managmt
Voltage
regulator
3.3 to 1.2 V
@VDD
Supply
supervision
POR/PDR
BOR
PVD
@VDDA
@VDD
XTAL OSC
4- 16MHz
IWDG
PWR
interface
@VBAT
XTAL 32 kHz
RTC
AWU
Backup register
4 KB BKPSRAM
TIM2
32b
TIM3
16b
TIM4
16b
TIM5
32b
TIM12
16b
TIM13
16b
TIM14
16b
USART2
smcard
irDA
USART3
smcard
irDA
UART4
UART5
SP2/I2S2
SP3/I2S3
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
bxCAN1
bxCAN2
CLK, NE [3:0], A[23:0],
D[31:0], OEN, WEN,
NBL[3:0], NL, NREG,
NWAIT/IORDY, CD
NIORD, IOWR, INT[2:3]
INTN, NIIS16 as AF
HSYNC, VSYNC
PUIXCLK, D[13:0]
DP
DM
ID, VBUS, SOF
VDD = 1.8 to 3.6 V
VSS
VCAP1, VCPA2
VDDA, VSSA
NRST
OSC_IN
OSC_OUT
VBAT = 1.65 to 3.6 V
OSC32_IN
OSC32_OUT
RTC_AF1
RTC_AF1
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
4 channels
2 channels as AF
1 channel as AF
1 channel as AF
RX, TX as AF
CTS, RTS as AF
RX, TX as AF
CTS, RTS as AF
RX, TX as AF
RX, TX as AF
MOSI/SD, MISO/SD_ext, SCK/CK
NSS/WS, MCK as AF
MOSI/SD, MISO/SD_ext, SCK/CK
NSS/WS, MCK as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
TX, RX
TX, RX
DAC1_OUT
as AF
DAC2_OUT
as AF
MS19920V3
1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to
APB1 are clocked from TIMxCLK either up to 84 MHz or 168 MHz, depending on TIMPRE bit configuration
in the RCC_DCKCFGR register.
2. The camera interface and ethernet are available only on STM32F407xx devices.
18/185
DocID022152 Rev 4
Share Link: 