STM32F407IGH6TR データシートの表示（PDF） - STMicroelectronics

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STM32F407IGH6TR

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

STM32F405xx, STM32F407xx

Figure 6. Multi-AHB matrix

64-Kbyte

CCM data RAM

ARM

Cortex-M4

GP

DMA1

GP

MAC USB OTG

DMA2 Ethernet HS

Description

2.2.8

S0 S1 S2

S3 S4 S5 S6 S7

M0 ICODE

M1 DCODE

Flash

memory

Bus matrix-S

M2

SRAM1

112 Kbyte

M3

SRAM2

16 Kbyte

M4

AHB1

peripherals

M5

AHB2

peripherals

M6

FSMC

Static MemCtl

APB1

APB2

ai18490c

DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8

streams each. They are able to manage memory-to-memory, peripheral-to-memory and

memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,

support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is

needed when the controller reaches the end of the buffer. The two DMA controllers also

have a double buffering feature, which automates the use and switching of two memory

buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software

trigger on each stream. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals:

• SPI and I2S

• I2C

• USART

• General-purpose, basic and advanced-control timers TIMx

• DAC

• SDIO

• Camera interface (DCMI)

• ADC.

DocID022152 Rev 4

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