CS4391(2000) データシートの表示（PDF） - Cirrus Logic

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CS4391
(Rev.:2000)

24-Bit, 192 kHz Stereo DAC with Volume Control

Cirrus Logic 

CS4391

6. PIN DESCRIPTION - DSD MODE

Reset

RST

1

Logic Voltage

VL

2

Channel A Data

DSD_A

3

Channel B Data

DSD_B

4

DSD Mode Select DSD_MODE

5

Master Clock

MCLK

6

DSD Serial Clock DSD_SCLK

7

Refer to PCM Mode (SCL/CCLK) M2

8

Refer to PCM Mode (SDA/CDIN) M1

9

Refer to PCM Mode (AD0/CS) M0

10

20 AMUTEC Refer to PCM Mode

19 AOUTA- Refer to PCM Mode

18 AOUTA+ Refer to PCM Mode

17 VA

Refer to PCM Mode

16 AGND

Refer to PCM Mode

15 AOUTB+ Refer to PCM Mode

14 AOUTB- Refer to PCM Mode

13 BMUTEC Refer to PCM Mode

12 CMOUT

Refer to PCM Mode

11 FILT+

Refer to PCM Mode

DSD Audio Data - DSD_A and DSD_B

Pins 3 and 4, Inputs

Function:

Direct Stream Digital audio data is clocked into DSD_A and DSD_B via the DSD serial clock.

DSD Mode - DSD_Mode

Pin 5, Input

Function:

This pin must be set to a logic ‘1’ and M0-M2 must be properly set to access the DSD Mode in Hardware

Mode. Refer to Table 19.

In Control Port Mode, this pin must be set to a logic ‘1’ and the Control Registers must be properly set to

access the DSD Mode. Refer to register descriptions.

Master Clock - MCLK

Pin 6, Input

Function:

The master clock frequency must be either 4x, 6x, 8x or 12x the DSD data rate for 64x oversampled DSD

data or 2x, 3x, 4x or 6x the DSD data rate for 128x oversampled DSD data.

DSD Serial Clock - DSD_SCLK

Pin 7, Input

Function:

Clocks the individual bits of the DSD audio data into the DSD_A and DSD_B pins.

DS335PP3

25

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