ADE3300 データシートの表示（PDF） - STMicroelectronics
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ADE3300 Datasheet PDF : 88 Pages
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ADE3XXX
Register Name
SRTXK_VSYNC_SEL
SRTXK_VSYNC_THR_L
SRTXK_VSYNC_THR_H
SRTXK_COAST_VS_SEL
SRTXK_COAST_RISE_L
SRTXK_COAST_RISE_M
SRTXK_COAST_RISE_H
SRTXK_COAST_FALL_L
SRTXK_COAST_FALL_M
SRTXK_COAST_FALL_H
SRTIK_HS_CTRL
SRTIK_VS_SEL
Sync Retiming Block
Table 12: Sync Retiming Registers (Sheet 2 of 2)
Addr
0x01E5
0x01E6
0x01E7
0x01E8
0x01E9
0x01EA
0x01EB
0x01EC
0x01ED
0x01EE
0x01F0
0x01F1
Mode Bits
R/W
[7:3]
[2:0]
R/W
R/W
R/W
R/W
[7:0]
[7:4]
[3:0]
[7:4]
[3]
R/W
[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:3]
[2]
R/W
[1:0]
[7:2]
R/W
[1:0]
Default
Description
0x0
0x080
Reserved
filtered vert sync source select
0x0: avsync pin
0x1: vsync from composite ahsync pin
0x2: vsync from composite acsync pin
0x3: Reserved
0x4: DVI vsync
0x5: YUV vsync
0x6 - 0x7: Reserved
filtered vert sync delay [7:0]
Reserved
filtered vert sync delay [11:8]
0x0
Reserved
0x0
coast signal trigger edge
0: posedge of selected vertical
1: negedge of selected vertical
0x0
source select for coast vert sync trigger
0x0: avsync pin
0x1: vsync from ahsync pin
0x2: vsync from acsync pin
0x3: Reserved
0x4: DVI vsync
0x5: YUV vsync
0x6: srt vsync (filtered vsync)
0x7: Reserved
0x0
rising edge of coast, in XCLKs from vsync
trigger
0x0
0x0
0x0
falling edge of coast, in XCLKs from vsync
trigger
0x0
0x0
0x0
Reserved
0x0
Resample clock edge to transfer hsync into
the INCLK domain; depends on LLK phase
offset value.
0: posedge INCLK
1: negedge INCLK
0x0
horz sync source select for resampling into
the INCLK domain
0x0: LLPLL lock sync (normal)
0x1: ahsync pin
0x2: acsync pin
0x3: Reserved
0x0
Reserved
0x0
vert sync source select for resampling
0x0: avsync pin
0x1: vsync from ahsync pin
0x2: vsync from acsync pin
0x3: srt vsync (filtered vsync)
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